Power integrated circuits, sometimes called high-voltage integrated circuits, constitute an important branch of the modern electronics, and can provide new types of circuits which feature high speed, high integration, low power consumption, and anti-irradiation for various power conversion and energy processing devices. Thus, they are widely applicable to the common consumption fields such as electric control systems, automotive electrics, display drivers, communications, and illumination, and applicable to other important fields such as national defense and aerospace. As applications thereof are increasingly popular, higher requirements are posed for the high-voltage devices in the core.
Power integrated circuits are usually combined with the high-voltage power transistor, control converter, monolithic logic functional devices, and the like, so high-voltage devices must be integrated with low-voltage logic devices on one chip. Silicon-on-insulator (SOI), as an ideal dielectric isolation material, can effectively isolate high-voltage modules from low-voltage modules and also isolate high-voltage devices from low-voltage devices, thus completely eliminating electrical interference and simplifying the design of the device structure. Meanwhile, the area of the SOI isolation region is smaller than that of the junction isolation, which greatly saves the die area, reduces the parasitic capacitance, and is convenient to integration of various circuits and devices. Therefore, application of the SOI technology is particularly advantageous in high-voltage devices and power integrated circuits, and has a wide application prospect.
IC products integrated with 600 V or above SOI high-voltage power devices are widely used in fluorescent lamps, switch power supply control, and the like. Compared with bulk-silicon SOI high-voltage devices, conventional SOI high-voltage devices can prevent extension of the depletion layer towards the substrate because of existence of the dielectric buried layer (BOX), and their vertical breakdown voltages are comparatively low. In general, design of 200 V or less SOI high-voltage devices is easier than that of 600 V or above SOI high-voltage devices.
The thickness of the top silicon of the SOI material has an effect on the critical breakdown electric field. When the silicon film is relatively thick (generally thicker than 1 μm), increased thickness will cause increased vertical breakdown voltage; however, when the silicon film is relatively thin (generally thinner than 1 μm), reduced thickness will cause decreased vertical breakdown voltage. Currently, the ideal fabricating method of 600 V or above SOI high-voltage devices is to adopt ultra-thin top silicon (0.2-0.5 μm thick), adopt shortened ionization integrating path to strengthen the vertical critical breakdown electric field of the silicon, and adopt linear doping of the drift region to realize uniform distribution of the electric field.
However, as the existing technique imposes a limit, the thickness of the top silicon of the SOI material is generally larger than 1 μm. In order to achieve the thickness of 0.2-0.5 μm, the technology of local oxidation of silicon, i.e. LOCOS, is developed. The existing technology has the following disadvantages: it takes a relatively long time to perform local oxidation of silicon to form a field oxide layer with the thickness of 2 μm, and the formed field oxide layer is obviously about 1 μm higher than the silicon top surface. As shown in FIG. 1, oxide layer 14 is formed in the local area of the SOI substrate (including bottom silicon 11, buried oxide layer 12, and top silicon 13), which is obviously higher than the upper surface of the SOI substrate. Although a polycrystalline silicon gate can be prolonged directly thereon to adjust the electric field of the drift region, the above-surface height readily has the impact on the accuracy of subsequent photoetching. Therefore, in order to solving the problem of the prior art, there is a need for a manufacturing method of SOI high-voltage power devices.